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EM640FV16FW series low power, 256kx16 sram 1 document title 256k x16 bit low power and low voltage full cmos static ram revision history revision no. history draft date remark 0.0 initial draft august 13 , 2003 emerging memory & logic solutions inc. 4f korea construction financial cooperative b/d, 301-1 yeon-dong, jeju-si, jeju-do, rep.of korea zip code : 690-719 tel : +82-64-740-1712 fax : +82-64-740-1749~1750 / homepage : www.emlsi.com the attached data sheets are provided by em lsi reserve the right to chan ge the specifications and produ cts. emlsi will answer t o your questions about device. if you have any questions, please cont act the emlsi office.
EM640FV16FW series low power, 256kx16 sram 2 features - process technology : 0.18 m full cmos - organization :256k x16 - power supply voltage => EM640FV16FW : 2.7~3.6v - three state output and ttl compatible - packaged product designed for 55/70ns general physical specifications - backside die surface of polished bare silicon - typical die thickness = 725um - typical top-level metalization : => metal ( ti/tin/al-cu 0. 5% ) : 5.7k angstroms thickness - topside passivation : => 7k angstroms pe-sin - typical pad size : 90.0um x 80.0um - wafer diameter : 8 inch options - c1/w1 : dc probed die/wafer @ hot temp - c2/w2 : dc/ac probed die/wafer @ hot temp 256k x16 bit low power and low voltage cmos static ram pad descriptions name function name function cs1 , cs2 chip select inputs vcc power supply oe output enable input vss ground we write enable input ub upper byte (i/o 9~16 ) a0~a17 address inputs lb lower byte (i/o 1~8 ) i/o1~i/o16 data inputs/outpus *nc no connection
EM640FV16FW series low power, 256kx16 sram 3 functional specifications there are 3 classifications for emlsi die and wafers products, which are c1 and c2 for die and w1 and w2 for wafer, respective ly. each die and wafer support dedicated charateristics and probe t he eletrical parameters within their specifications. followings are brief information for die and wafer classifications. please refe r to packaged specifications for more information but these par ameters are not guaranteed at bare die and wafer. ? c1 level die or w1 level wafer the dc parameters are measured by specification for c1 level die or w1 level wafer. the dc parameters measured at 70 c tem- perature, which called ? hot dc sorting ? other parameters are not guaranteed and warranted including device reliability. please refer to qualification report for device reliability and package level datasheets for electrical parameters. ? c2 level die or w2 level wafer the dc parameters and selected ac parameters are measured with fo r c2 level die or w2 level wafer. the dc characteristics of c2 die and w2 wafer is tested based on dc specif ications of c1 level die and w1 level wafer. the dc and specified ac parameters ar e tested at 70 c temperature, which called ? hot dc & selective ac sorting ? . other parameters are not guaranteed and warranted including device reliability. please refer to qualification repo rt for device reliability and package level datasheets for elec trical param- eters. c2 level die and w2 level wafer probe following ac parameter. ? trc, taa, tco ? twc, tcw packaging individual device will be packed in anti-static trays. ? chip trays : a 2-inch square waffle style carrier for die with separate compartments for each die. commonly referred to as a wa ffle pack, each tray has a cavity size selected for the device that allows for easy loading and unloading a nd prevents rotation. the tray itself is made of conductive material to reduc e the danger of damage to the die fro m electrostatic discharge. the chip carriers will be labeled with the following information : ? emlsi wafer lot number ? emlsi part number ? quantity ? jar packing : jar packing is made by emlsi and used by many cust omers that we deliver the request ed die as wafer. the pack is consisted of clean paper to wrap the wafer, high cushioned s ponge between wafers and hardly fr agile plastic box with sponge. ea ch pack has typically 25 wafers and then several packs ar e put into larger box depending on amounts of wafers. storage and handling emlsi recommends the die stored in a controlled environment with filtered nitrogen. the carrier must be opened at esd safe environment when inspection and assembly. bond pad #1 at top die orientation in chip carriers
EM640FV16FW series low power, 256kx16 sram 4 functional description note: x means don?t care. (must be low or high state) cs 1 cs 2 oe we lb ub i/o 1-8 i/o 9-16 mode power h x x x x x high-z high-z deselected stand by x l x x x x high-z high-z deselected stand by x x x x h h high-z high-z deselected stand by l h h h l x high-z high-z output disabled active l h h h x l high-z high-z output disabled active l h l h l h data out high-z lower byte read active l h l h h l high-z data out upper byte read active l h l h l l data out data out word read active l h x l l h data in high-z lower byte write active l h x l h l high-z data in upper byte write active l h x l l l data in data in word write active absolute maximum ratings * * stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. functional operation should be restricted to recommended operating condition. exposure to absolute maximum rating conditions for extended periods may affect reliability. parameter symbol ratings unit voltage on any pin relative to vss v in , v out -0.2 to vcc+0.3(max.4.0v) v voltage on vcc supply relative to vss v cc -0.2 to 4.0v v power dissipation p d 1.0 w operating temperature t a -40 to 85 o c
EM640FV16FW series low power, 256kx16 sram 5 dc and operatin g characteristics notes 1. typical values are measured at vcc=3.3v, t a = 25 o c and not 100% tested. parameter symbol test conditions min typ max unit input leakage current i li v in =v ss to v cc -1 - 1 ua output leakage current i lo cs 1 =v ih or cs 2 =v il or oe =v ih or we =v il or lb =ub =v ih v io =v ss to v cc -1 - 1 ua operating power supply i cc i io =0ma, cs 1 =v il , cs 2 =we =v ih , v in =v ih or v il --3ma average operating current i cc1 cycle time=1 s, 100% duty, i io =0ma, cs 1 < 0.2v, lb < 0.2v or/and ub < 0.2v, cs 2 > v cc -0.2v, v in < 0.2v or v in > v cc -0.2v --3 ma i cc2 cycle time = min, i io =0ma, 100% duty, cs 1 =v il , cs 2 =v ih, lb =v il or/and ub =v il , v in =v il or v ih 55ns - - 30 ma 70ns - - 25 ma output low voltage v ol i ol = 2.1ma --0.4v output high voltage v oh i oh = -1.0ma 2.4 - - v standby current (ttl) i sb cs 1 =v ih , cs 2 =v il , other inputs=v ih or v il --0.3ma standby current (cmos) i sb1 cs 1 > v cc -0.2v, cs 2 > v cc -0.2v (cs 1 controlled) or 0v< cs 2 < 0.2v (cs 2 controlled), other inputs = 0~v cc (typ. condition : v cc =3.3v @ 25 o c) (max. condition : v cc =3.6v @ 85 o c) ll - 1 1) 12 ua recommended dc operating conditions 1) 1. ta= -40 to 85 o c, otherwise specified 2. overshoot: v cc +2.0 v in case of pulse width < 20ns 3. undershoot: -2.0 v in case of pulse width < 20ns 4. overshoot and undershoot are sampled, not 100% tested . parameter symbol min typ max unit supply voltage v cc 2.7 3.3 3.6 v ground v ss 000 v input high voltage v ih 2.2 - v cc + 0.2 2) v input low voltage v il -0.2 3) -0.6v capacitance 1) (f =1mhz, t a =25 o c) 1. capacitance is sa mpled, not 100% tested item symbol test condition min max unit input capacitance c in v in =0v - 8 pf input/ouput capacitance c io v io =0v - 10 pf
EM640FV16FW series low power, 256kx16 sram 6 ac operating conditions test conditions ( test load and test input/output reference) input pulse level : 0.4 to 2.2v input rise and fall time : 5ns input and output reference voltage : 1.5v output load (see right) : cl = 100pf+ 1 ttl cl 1) = 30pf + 1 ttl 1. including scope and jig capacitance 2. r 1 =3070 ohm , r 2 =3150 ohm 3. v tm =2.8v cl 1) v tm 3) r 1 2) r 2 2) parameter symbol 55ns 70ns unit min max min max read cycle time t rc 55 - 70 - ns address access time t aa -55-70 ns chip select to output t co1, t co2 -55-70 ns output enable to valid output t oe -30-35 ns ub , lb acess time t ba 55 70 ns chip select to low-z output t lz1, t lz2 10 - 10 - ns ub , lb enable to low-z output t blz 10 - 10 - ns output enable to low-z output t olz 5-5- ns chip disable to high-z output t hz1, t hz2 020025 ns ub , lb disable to high-z output t bhz 020025 ns output disable to high-z output t ohz 020025 ns output hold from address change t oh 10 - 10 - ns parameter symbol 55ns 70ns unit min max min max write cycle time t wc 55 - 70 - ns chip select to end of write t cw1, t cw2 45 - 60 - ns address setup time t as 0- 0 -ns address valid to end of write t aw 45 - 60 - ns ub , lb valid to end of write t bw 45 - 55 - ns write pulse width t wp 40 - 50 - ns write recovery time t wr 0- 0 -ns write to ouput high-z t whz 0 20 0 25 ns data to write time overlap t dw 30 30 ns data hold from write time t dh 0- 0 -ns end write to output low-z t ow 5- 5 -ns read cycle (v cc =2.7 to 3.6v, gnd = 0v, t a = -40 o c to +85 o c) write cycle (v cc =2.7 to 3.6v , gnd = 0v, t a = -40 o c to +85 o c)
EM640FV16FW series low power, 256kx16 sram 7 t rc address cs1 cs2 ub ,lb oe data out t co t oh t ba t oe high-z t bhz t ohz t whz timing waveform of read cycle(2) (we = v ih ) data valid t olz t blz t lz t aa t hz t rc address t aa data valid t oh previous data valid timing waveform of read cycle(1). (address controlled, cs 1=oe =v il , cs2=we =v ih, ub or/and lb = v il ) data out timing diagrams notes (read cycle) 1. t hz and t ohz are defined as the outputs achieve the open circuit condi tions and are not referanced to output voltage levels. 2. at any given temperature and voltage condition, t hz (max.) is less than t lz (min.) both for a given device and from device to device interconnection.
EM640FV16FW series low power, 256kx16 sram 8 t wr (4) t wc address cs1 cs2 ub ,lb we data in data out t cw (2) t aw t bw t wp (1) t as (3) high-z t dw t dh high-z t ow t whz data undefined timing waveform of write cycle(1) (we controlled) data valid t wc address cs1 cs2 ub ,lb we data in data out t cw (2) t wr (4) t aw t bw t wp (1) t dw t dh timing waveform of write cycle(2) (cs1 controlled) t as (3) high-z high-z data valid
EM640FV16FW series low power, 256kx16 sram 9 t wc address cs1 cs2 ub ,lb we data in data out t cw (2) t wr (4) t aw t bw t wp (1) t dw t dh timing waveform of write cycle(3) (ub , lb controlled) high-z high-z data valid t as (3) notes (write cycle) 1. a write occurs during the overlap(t wp ) of low cs 1 and low we . a write begins when cs 1 goes low and we goes low with asserting ub or lb for single byte operation or simultaneously asserting ub and lb for double byte operation. a write ends at the earliest transition when cs 1 goes high and we goes high. the t wp is measured from the beginni ng of write to the end of write. 2. t cw is measured from the cs 1 going low to end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end or write to the address change. t wr applied in case a write ends as cs 1 or we going high.
EM640FV16FW series low power, 256kx16 sram 10 data retention characteristics notes 1. see the i sb1 measurement condition of datasheet page 5. parameter symbol test condition min typ max unit v cc for data retention v dr i sb1 test condition (chip disabled) 1) 1.5 - 3.6 v data retention current i dr v cc =1.5v, i sb1 test condition (chip disabled) 1) -0.5-ua chip deselect to data retention time t sdr see data retention wave form 0-- ns operation recovery time t rdr t rc -- t sdr t rdr data retention mode cs 1 > vcc-0.2v v cc 2.7v 2.2v v dr cs 1 gnd t sdr t rdr data retention mode v cc 2.7v cs 2 v dr 0.4v gnd cs 2 < 0.2v data retention wave form
EM640FV16FW series low power, 256kx16 sram 11 em x xx x x x xx x x - xx xx memory function guide 1. emlsi memory 2. device type 3. density 5. technology 6. operating voltage 8. version 9. packages 10. speed 7. orgainzation 1. memory component 2. device type 6 ------------------------ low power sram 7 ------------------------ stram 3. density 1 ------------------------- 1m 2 ------------------------- 2m 4 ------------------------- 4m 8 ------------------------- 8m 16 ----------------------- 16m 32 ----------------------- 32m 64 ----------------------- 64m 4. mode option 0 -------- dual cs 1 -------- single cs 2 -------- multiplexed address 3 -------- single cs with lb ,ub (tba=toe) 4 -------- single cs with lb ,ub (tba=tco) 5 -------- dual cs with lb ,ub (tba=toe) 6 -------- dual cs with lb ,ub (tba=tco) 5. technology blank ------------------ cmos f ------------------------ full cmos 6. operating voltage blank ------------------- 5v v ------------------------- 2.7v~3.6v u ------------------------- 3.0v s ------------------------- 2.5v r ------------------------- 2.0v p ------------------------- 1.8v 4. option 11. power 7. orginzation 8 ---------------------- x8 bit 16 ---------------------- x16 bit 32 ---------------------- x32 bit 8. version blank ----------------- mother die a ----------------------- first revision b ----------------------- second revision c ----------------------- third revision d ----------------------- fourth revision e ----------------------- fifth revision f ----------------------- sixth revision 9. package blank ---------------------- fpbga s ---------------------------- 32 stsop1 t ---------------------------- 32 tsop1 u ---------------------------- 44 tsop2 w ---------------------------- wafer 10. speed 45 ---------------------- 45ns 55 ---------------------- 55ns 70 ---------------------- 70ns 85 ---------------------- 85ns 10 --------------------- 100ns 12 --------------------- 120ns 11. power ll ---------------------- low low power l ---------------------- low power s ---------------------- standard power

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